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STEC is
committed to technology, development, and innovation through
extensive investment in R & D. Our R & D focus is developing
a leading-edge flash controller capable to overcome the limitations
of flash components in terms of reliability, endurance, protection,
maintenance, security, and performance. |
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individual blocks in a NAND flash device are limited in
the number of Program/Erase Cycles they can sustain before
the probability of errors rise to unacceptable levels.
It is therefore extremely important that all blocks within
a flash chip are aging in the same manner. If one area
gets written to frequently, while another gets never touched,
the lifetime of the entire flash is impacted.
To overcome this limitation, a flash file system needs
to be implemented to make sure that with any new write
operation, the youngest block is used. STEC's implemented
wear leveling scheme spreads flash media usage evenly
across all pages, thereby maximizing flash lifetime. |
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STEC has implemented in its existing generation of
controllers an Error Correction scheme, based on the
Reed Solomon algorithm. The implemented scheme allows
for detection up to 5 bytes per 512 bytes page and correction
up to 4 bytes per 512 bytes page, regardless where these
errors occur within the page. Error Correction is implemented
as follows:
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1. |
Every time data is written to the
flash, STEC's flash controller passes the data block
through the ECC engine to create a unique ECC signature; |
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The data and ECC signature stored
together on the flash; |
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When reading the data back, both the
data and originally stored ECC signature are read
into the buffer of the NAND controller. A new ECC
signature is generated, based upon the data portion; |
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The newly created ECC signature is
compared to the original ECC signature. If both
signatures are the same, no bit flip has occurred,
and the data will be provided to the host. If the
two 2 signatures differ, the data needs to be corrected
before given back to the host. |
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Due to the need to keep cost low and yields high, NAND
flash devices are shipped from the NAND manufacturer's
fab with up to 2% randomly scattered Bad Blocks. In
addition to the initial Bad Blocks, new Bad Blocks are
created during operation when the amount of bit flips
in page exceed the number that can be corrected by the
ECC engine. The block where that page is located will
become invalid and no longer usable (Bad Block).
STEC's Bad Block Management makes sure that both the
initial Bad Blocks, as well blocks that show non-recoverable
errors during device operation, are mapped out. This
not only ensures data integrity, but also enhances performance
by eliminating the need for repeated write operations
as a result data being repeatedly mapped to the same
Bad Block. This management process is completely transparent
to the applications. |
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STEC has developed an innovative technique to avoid
data loss or corruption in case of power loss, called
Power Down Recovery.
During the course of each write operation, the controller
maintains multiple flags and pointers to monitor the
start and end of each phase. Both are used to monitor
the write/erase progress and show which phase of the
process has been completed or is in progress. If the
operation is interrupted by a power failure, the controller
will use the pointers to indicate the last block that
was accessed. By reading the start and completion flags
on that block, the controller will be able to detect
where a sector write was interrupted.
In case the page only shows the start flag, but not
the completion flag, the controller will consider the
data as not reliable. As such, all the data of that
block, apart from the uncompleted sector, will be transferred
to a new block. The old block will be erased and transferred
to the pool of spare blocks. This mechanism protects
the original data from being overwritten by incomplete
or corrupted data. |
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